1. Field of the Invention
The present invention relates to a bias voltage generation circuit for use in a semiconductor memory device wherein a stable bias must be applied to the substrate (including well regions therein).
2. Description of the Related Art
In a DRAM, a negative potential is applied to the substrate's internal regions corresponding to the back gate of an N-type transistor (namely, the substrate itself and the well regions formed therein), so as to control the threshold of the N-type transistor. The bias level VBB is applied not by an external power supply but by a bias voltage generation circuit located inside the chip. In some cases, the bias level VBB may become close to 0V, due to the operation of the circuits formed on the substrate. If the bias level VBB is high, the threshold of the N-type transistor will vary, resulting in an increase in the amount of leak current. If the bias level VBB is as high as 0V, it is likely that a latch-up phenomenon will occur. The time when a maximum amount of current is generated in the substrate is the time where the data in memory cells are accessed. Since a large number of transistors simultaneously operate at the time, the bias level VBB rises and becomes close to 0V.
FIG. 1 is a circuit diagram showing a conventional substrate bias generation circuit. The substrate bias generation circuit comprises a VBB detector 11, a ring oscillator 12, and a charge pump circuit 13 for generating a negative voltage, and biasing a P-type region 14 in the substrate to be a predetermined negative potential.
The charge pump circuit 13 is driven by the oscillation frequency of the ring oscillator 12 and generates a bias level VBB. In the bias voltage generation circuit, the VBB detector 11 is connected to the input terminal of the ring oscillator 12 and stops the oscillation of the ring oscillator 12 when the bias level VBB reaches a predetermined potential level.
As is shown in FIG. 1, the VBB detector 11 includes a detection circuit 15 for determining whether the bias level VBB is a normal value or not, and a delay circuit 16. The detection circuit 15 is made up of P-channel MOS transistor TR1, N-channel MOS transistors TR2-TR7, and P-channel MOS transistor TR8. The current paths of these MOS transistors TR1-TR8 are connected in series. The N-channel transistors TR2-TR7 are applied with gate voltages for maintaining them to be in a conductive state. At the connection node N1 located between the current paths of transistors TR1 and TR2, a VBB monitor level appears, which corresponds to the potential difference between a power supply voltage VCC and the bias level VBB. The delay circuit 16 is made up of inverters INV1-INV5.
When the power supply is switched on, the power supply voltage VCC is applied to the VBB detector 11, and transistor TR1 is turned on. Since, at the time, the bias level VBB is in the floating state, transistors TR2-TR8 remain in the OFF state. Therefore, the VBB monitor level at the connection node N1 is "H". A signal due to this VBB monitor level passes through the delay circuit 16 and causes the output of the delay circuit 16 to become "L" in level. Then, this output of the delay circuit 16 causes the output of inverter INV6 to become "H" in level, thereby starting the oscillation of the ring oscillator 12. After the bias level VBB reaches the predetermined potential level, the VBB monitor level at the connection node N1 is "L". In this case, the output of the VBB detector 11 is set to be "L" in level by both the delay circuit 16 and inverter INV6, thereby stopping the oscillation of the ring oscillator 12.
In the circuit configuration mentioned above, the amount of current consumed is large when the ring oscillator 12 is frequently switched between ON and OFF. Therefore, the VBB detector 11 is made to comprise the delay circuit 16 so as not to be too sensitive after the bias level VBB reaches the predetermined potential level. In addition, the delay circuit 16 is designed to suppress a rush current since it is supplied with a signal having a very obtuse waveform. To be more specific, transistors TR19 and TR20 located on the side of the P-channel MOS transistors are connected in series with each other, so as to cause transistor TR20 to serve as a resistor, as is shown in FIG. 1. This circuit configuration operates in a satisfactory manner when the bias level VBB rises gradually, but does not when the bias level VBB rises momentarily.
In the case of a DRAM, the amount of current flowing in the substrate becomes largest when a memory cell is activated in response to the determination of a row address. In particular, in the case where the DRAM is of a multi-bit structure, the number of memory cell arrays is large. Therefore, the bias level VBB rises momentarily, and the restart time of the charge pump circuit 13 is inevitably delayed.